(1) Technical Field
This invention relates generally to an apparatus and method for polishing semiconductor wafers during the manufacturing of integrated circuit, and more particularly, to methods for dressing a polishing pad during the process of chemical mechanical polishing.
(2) Description of the Prior Art
The following five documents relate to methods dealing with the dressing of chemical mechanical polishing (CMP) pads during the polishing of integrated circuits formed on semiconductor wafers.
U.S. Pat. No. 5,681,212 issued Oct. 28, 1997 to H. Hayakawa et al., shows a polish head.
U.S. Pat. No. 5,664,987 issued Sep. 9, 1997 to P. Renteln, discloses a method and apparatus to condition a polish pad using a conditioning track on the polish pad.
U.S. Pat. No. 5,624,299 issued Apr. 29, 1997 to Shendon, shows a carrier head with a polish pad and retaining ring.
U.S. Pat. No. 5,616,063 issued Apr. 1, 1997 to K. Okumura et al. shows a polishing apparatus with multiple heads.
U.S. Pat. No. 5,605,499 issued Feb. 25, 1997 to M. Suglyama et al. shows a standard chemical mechanical polishing head.
The fabrication of integrated circuits on a semiconductor wafer involves a number of steps where patterns are transferred from photolithographic photomasks onto the wafer. The photomasking processing steps opens selected areas to be exposed on the wafer for subsequent processes such as inclusion of impurities, oxidation, or etching.
During the forming of integrated circuit structures, it has become increasingly important to provide structures having multiple metallization layers due to the continuing miniaturization of the circuit elements in the structure. Each of the metal layers is typically separated from another metal layer by an insulation layer, such as an oxide layer. To enhance the quality of an overlying metallization layer, one without discontinuities of other blemishes, it is imperative to provide an underlying surface for the metallization layer that is ideally planar. The process of planarizing is now a standard process application of integrated circuit manufacturers.
Plasma, or reactive ion etching of the oxide layers having a resist planarizing medium, are conventional planarization techniques that are used to provide a smooth surface and a local planarization with a range of 1 um.
To meet the demand for larger scale integration, and more metal and oxide layers in devices and the exacting depth of focus needed for submicron lithography, a new planarization method known as chemical mechanical polishing (CMP), was developed and is presently used by most major semiconductor manufacturers. CMP planarization of a wafer involves supporting and holding the wafer against a rotating polishing pad wet with a polishing slurry and at the same time applying pressure. Unlike the conventional planarization techniques, CMP provides a substantially improved overall planarization, that is, an improvement of 2 to 3 orders of magnitude over conventional methods. Although CMP planarization is effective, one recurring problem with CMP processing is the tendency of the process to differentially polish the surface of the wafer and thereby create localized over-polished and under-polished areas across the wafer surface. Where the wafer is to be further processed, such as by photolithographic etching to create integrated circuit structures, thickness variation in the planarized layer makes it extremely difficult to meet the fine resolution tolerances required to provide high yield of functional die on a wafer.
The difficulty in controlling the polishing process is maintaining the oxide removal rate constant across the top surface of the wafer as well as maintaining a constant oxide removal rate from one wafer to the next, when wafers are processed in succession. One known method of adjusting the oxide removal rate is by reconditioning the surface state of the polishing pad. This reconditioning process is known in the semiconductor industry as "dressing". Dressing consists of abrading the surface of the polishing pad with a grit-type instrument, much like a rasp having a diamond abrasive, between the polishing of successive wafers or successive groups of wafers. This dressing removes the glazed, hardened surface on the polishing pad and reconditions its polishing surface thereby maintaining a relatively constant removal rate from wafer to wafer. Without such dressing, or in the alternative, without repeatedly changing the polishing pad, the oxide removal rate would continue to degrade as more wafers are polished, since the surface roughness tends to decrease and such roughness determines, in large part, the overall abrasiveness of the polishing pad and slurry. The polishing pad itself, however, provides no significant abrasive effect without the use of the abrasive slurry even when the polishing pad is fully conditioned.
Prior dressing techniques do not provide trouble free process control for producing device patterns. Oxide removal rate is not constant between wafer and thus, causes a problem that the process margin in fabricating semiconductor devices is reduced, so as to lower production yield.